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| 4M x 16-Bit Dynamic RAM (8k, 4k & 2k Refresh, EDO-Version) Advanced Information * * * * HYB 3164165AT(L) -40/-50/-60 HYB 3165165AT(L) -40/-50/-60 HYB 3166165AT(L) -40/-50/-60 4 194 304 words by 16-bit organization 0 to 70 C operating temperature Hyper Page Mode - EDO - operation Performance: -40 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/write cycle time Hyper page mode (EDO) cycle time 40 10 20 69 16 -50 50 13 25 84 20 -60 60 15 30 104 25 ns ns ns ns ns * * Single + 3.3 V ( 0.3V) power supply Low power dissipation: -40 HYB3166165AT(L) HYB3165165AT(L) HYB3164165AT(L) 1008 756 612 -50 612 504 324 -60 450 360 324 mW mW mW * * * * * 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 A standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only 2 CAS / 1 WE byte control 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT) 2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT) 256ms refresh period for L-versions Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on an advanced first generation 64Mbit 0,35 m CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)165AT operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165AT to be packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5/6)165ATL parts have a very low power sleep mode" supported by Self Refresh. Ordering Information Type 8k-refresh versions: HYB 3164165AT-40 HYB 3164165AT-50 HYB 3164165AT-60 HYB 3164165ATL-50 HYB 3164165ATL-60 4k-refresh versions: HYB 3165165AT-40 HYB 3165165AT-50 HYB 3165165AT-60 HYB 3165165ATL-50 HYB 3165165ATL-60 2k-refresh versions: HYB 3166165AT-40 HYB 3166165AT-50 HYB 3166165AT-60 HYB 3166165ATL-50 HYB 3166165ATL-60 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil EDO-DRAM (access time 40 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil EDO-DRAM (access time 40 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil EDO-DRAM (access time 40 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) EDO-DRAM (access time 50 ns) EDO-DRAM (access time 60 ns) Ordering Code Package Descriptions Semiconductor Group 2 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Pin Configuration P-TSOPII-50 (400 mil) O VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C. VCC WE RAS N.C. N.C. N.C. N.C. A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 . 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C. VSS . LCAS UCAS OE N.C. N.C. A12/N.C. * A11/N.C.** A10 A9 A8 A7 A6 VSS * Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L) ** Pin 32 is A11 for HYB 3164(5)165AT(L) and N.C. for HYB 3166165AT(L) Pin Names A0-A12 A0-A11 A0-A10 RAS OE I/O1-I/O16 UCAS, LCAS WE Vcc Vss Address Inputs for 8k-refresh version HYB 3164165T(L) Address Inputs for 4k-refresh version HYB 3165165T(L) Address Inputs for 2k-refresh version HYB 3166165T(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground Semiconductor Group 3 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM TRUTH TABLE FUNCTION Standby Read:Word Read:Lower Byte Read:Upper Byte Write:Word (Early-Write) Write:Lower Byte (Early-Write) Write:Upper Byte (Early Write) Read-ModifyWrite Hyper Page Mode 1st Read (Word) Cycle Hyper Page Mode 2nd Read (Word) Cycle Hyper Page Mode 1st Early Write(Word) Cycle Hyper Page Mode 2nd Early Write(Word) Cycle Hyper Page Mode 1st RMW Cycle Hyper Page Mode 2st RMW Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh (Read) Hidden Refresh (Write) Self Refresh (L-version only) RAS LCAS UCAS WE H L L L L L L L L L L L L L L H-X L L H L L H L H-L H-L H-L H-L H-L H-L H H-X H H L L H L L H-L H-L H-L H-L H-L H-L H L L L L H X H H H L L L H-L H H L L H-L H-L X H L H L X OE X L L L X X X ROW ADD X ROW ROW ROW ROW ROW ROW COL ADD X COL COL COL COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL X I/O1I/O16 High Impedance Data Out Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data In Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In High Impedance L - H ROW L L X X ROW n/a ROW n/a L - H ROW L - H n/a X X X L X X ROW X X ROW ROW X H-L L H-L L L-H- L L L-H- L L H-L L Semiconductor Group 4 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS . . & Data in Buffer No. 2 Clock Generator 16 Data out Buffer 16 OE 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Column Address Buffer(9) 9 Column Decoder Refresh Controller Sense Amplifier I/O Gating 16 Refresh Counter (13) 13 Row 13 512 x16 Address Buffers(13) 13 Decoder 8192 Row Memory Array 8192x512x16 RAS No. 1 Clock Generator Block Diagram for HYB 3164165AT(L) Semiconductor Group 5 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS . . & Data in Buffer No. 2 Clock Generator 16 Data out Buffer 16 OE 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 Column Address Buffer(10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 16 Refresh Counter (12) 12 Row 1024 x16 Address Buffers(12) 12 Decoder 4096 Row Memory Array 4096x1024x16 RAS No. 1 Clock Generator Block Diagram for HYB 3165165AT(L) Semiconductor Group 6 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS . . & Data in Buffer No. 2 Clock Generator 16 Data out Buffer 16 OE 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 Column Address Buffer(11) 11 Column Decoder Refresh Controller Sense Amplifier I/O Gating 16 Refresh Counter (11) 11 Row 2048 x16 Address Buffers(11) 11 Decoder 2048 Row Memory Array 2048x2048x16 RAS No. 1 Clock Generator Block Diagram for HYB3166165AT(L) Semiconductor Group 7 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.3 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input (0 V < Vin < Vcc , all other pins = 0 V Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 - Unit Note V V V V V V A A 1) 1) VIH VIL VOH VOL VOH VOL II(L) IO(L) Vcc-0.2 -2 -2 0.2 2 2 Output leakage current (DO is disabled, 0 V < Vout < Vcc ) Semiconductor Group 8 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM DC-Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Operating Current -40 ns version -50 ns version -60 ns version Symbol refresh version 2k 4k 170 140 115 2 170 140 115 8k 125 100 85 2 125 100 84 mA mA mA mA mA mA mA 2) 3) 4) Unit Note ICC1 280 230 185 - (RAS, CAS, address cycling: tRC = tRC min.) Standby Current (RAS=CAS= Vih) RAS Only Refresh Current: -40 ns version -50 ns version -60 ns version ICC2 ICC3 2 280 230 185 - 2) 4) (RAS cycling: CAS = VIH: tRC = tRC min.) Hyper Page Mode (EDO) Current: ICC4 -40 ns version -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: tHPC=tHPC min.) 140 105 85 900 200 140 105 85 900 200 140 105 85 900 200 mA mA mA A A 2) 3) 4) Standby Current (RAS=CAS= Vcc-0.2V) ICC5 ICC5 - - Standby Current (L-Version) (RAS=CAS= Vcc-0.2V) CAS Before RAS Refresh Current ICC6 -40 ns version -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC min.) 280 230 185 400 170 140 115 400 170 140 115 400 mA mA mA A 2) 4) Self Refresh Current (L-version only) (CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) ICC7 Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit CI1 CI2 CIO Semiconductor Group 9 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol AC64-2E Limit Values - 40 min. max. Unit Note - 50 min. max. - 60 min. max. Common Parameters Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT 69 40 6 25 6 0 5 0 5 9 7 6 32 5 1 - - - - 100k 100k 84 50 8 30 8 0 7 0 7 11 9 8 40 5 1 - - - - 100k 100k 104 60 10 40 10 0 10 0 10 14 12 10 48 - 100k 100k ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 7 - - - - - - 30 20 - - - 50 128 64 256 - - - - - - 37 25 - - - - - - 45 30 - - - 50 128 64 256 - 50 128 64 256 5 1 - - - Refresh period for 8k-refresh-version tREF Refresh period for 4k-refresh version tREF Refresh period for L-versions tREF Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time tRAC tCAC tAA tOEA tRAL tRCS tRCH - - - - 20 0 0 40 10 20 10 - - - - - - - 25 0 0 50 13 25 13 - - - - - - - 30 0 0 60 15 30 15 - - - ns ns ns ns ns ns ns 11 8, 9 8, 9 8,10 Semiconductor Group 10 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol AC64-2E Limit Values - 40 min. max. Unit Note - 50 min. max. - 60 min. max. Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay tRRH tCLZ tOFF tDZC tDZO tCDD tODD 0 0 0 0 0 0 10 10 - - 10 10 - - - - 0 0 0 0 0 0 13 13 - - 13 13 - - - - 0 0 0 0 0 0 15 15 - - 15 15 - - - - ns ns ns ns ns ns ns ns 11 8 12 12 13 13 14 14 Output buffer turn-off delay from OE tOEZ Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 5 5 0 6 6 0 5 - - - - - - - 7 7 0 8 8 0 7 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15 Read-modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 89 52 22 32 5 - - - - - 109 65 28 40 7 - - - - - 133 77 32 47 10 - - - - - ns ns ns ns ns 15 15 15 Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time tHPC tCPA tCOH 16 - 3 - 22 - 20 - 5 - 27 - 24 - 5 - 32 - ns ns ns 7 Semiconductor Group 11 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol AC64-2E Limit Values - 40 min. max. 200k Unit Note - 50 min. max. 200k - 60 min. max. 200k RAS pulse width in hyper page mode tRAS CAS precharge to RAS Delay OE pulse width OE hold time from CAS high OE setup time prior to CAS tRHPC tOEP tOEHC tOES 40 22 5 5 0 5 50 27 5 5 0 5 60 32 5 5 0 5 ns ns ns ns ns ns - - - 10 - - - - 13 - - - - 15 - Output buffer turn-off delay from WE tWEZ Hyper Page Mode (EDO) Readmodify-Write Cycle Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 44 34 - - 54 42 - - 63 49 - - ns ns CAS before RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 5 5 5 5 5 - - - - - 5 5 5 5 5 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns Self Refresh Cycle (L-versions only) RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k 100k _ - - 100k _ - - ns ns ns 17 17 17 69 -50 - - 84 -50 104 -50 Semiconductor Group 12 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Notes: 1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a Hyper page mode cycle ( thpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh Semiconductor Group 13 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCRP UCAS LCAS V IH VIL tRAD tASR tASC AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tCAH Column tASR AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V Address AAAAAAA IH AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA VIL Row Row tRCH tRAH tRCS tRRH tAA tOEA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V WE AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL V OE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC tDZO tODD tCAC tCLZ Hi Z tCDD I/O (Inputs) V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tOFF tOEZ AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA I/O (Outputs) V V OH OL AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Valid Data Out Hi Z tRAC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL1 Read Cycle Semiconductor Group 14 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCAH Column tCRP UCAS LCAS V IH VIL tRAD tASR tASC AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tASR AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA V . Row Address IH Row VIL tRAH V tWCS t WP tCWL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH WE IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS I/O (Inputs) V IH VIL tDH Valid Data In OH I/O (Outputs) V OL V Hi Z AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA "H" or "L" WL2 Write Cycle (Early Write) Semiconductor Group 15 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tRAL tCRP UCAS LCAS V IH VIL tRAD tASR tASC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA tCAH Column tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAAAA Row AAAAAAAAA AAAAAAAAA IL AAAAAAAAA V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA . Row tRAH V WE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tRWL tWP AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA VIL tDZO tDZC I/O (Inputs) V IH AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA tODD tDS tOEZ AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tDH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL Valid Data tCLZ tOEA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I/O (Outputs) V V OH OL Hi-Z Hi-Z AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL3 Write Cycle (OE Controlled Write) Semiconductor Group 16 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRWC tRAS V tRP RAS IH VIL tCSH tRCD tRSH tCAS tCRP UCAS LCAS V IH VIL tRAH tASR V tCAH tASC tASR Row Address IH AAAA AAAA AAAA AAAA AAAA AAAA VIL Row AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column tRAD V AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tAWD tCWD tRWD tRWL tWP WE AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA tAA tRCS V tOEA tOEH AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA OE IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZO tDZC V AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tDS tDH Valid Data in AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA I/O (Inputs) tCLZ tCAC tODD tOEZ AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA Out AAAAAA I/O (Outputs) V OL V OH tRAC AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 17 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRAS V tRP tRHCP tRSH RAS IH tRCD VIL tCRP UCAS LCAS V IH tHPC tCAS tCRP tCP tCAS tCAS VIL tCSH tASR tRAH tASC AAA AAA tRAL tCAH tASC tCAH tASC tCAH AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA Address V AAAAA IH AAAAA VIL AAAAA AAAAA AAAAA AAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA tRAD tRRH tRCH AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tRCS WE VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tOES V tCAC tAA tCPA tCAC tAA tCPA tOFF AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA OE OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA V tRAC tAA tCAC I/O IH (Output) V IL V tOEZ tCOH AAAA AAAA AAAA AAAA AAAA AAAA AAAA tCOH Data Out 2 AAA AAA AAA AAA AAA AAA AAA tCLZ AAAA AAAA AAAA AAAA AAAA AAAA AAAA Data Out 1 Data Out N AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA WL5 "H" or "L" Hyper Page Mode (EDO) Read Cycle Semiconductor Group 18 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS UCAS LCAS VIL tCSH tASR tRAH tASC AAA AAA tRAL tCAH tASC tCAH tASC tCAH AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA Address V AAAAA IH AAAAA VIL AAAAA AAAAA AAAAA AAAAA AAA AAA Row AAA Column 1 AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAA tRAD tRRH tRCH tCAC tAA tCPA tOEHC tOEHC AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA tRCS WE VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tOES t V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA OEA OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCAC tAA tCPA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tOFF OE tRAC tAA tCAC I/O IH (Output) V IL V tOEP tOEZ tOEA tOEP tOEA tOEZ AAA AAA AAA AAA AAA AAA AAA tOEZ tCLZ AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Data Out 1 Data Out 2 AAA AAA AAA AAA AAA AAA AAA Data Out N AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA WL6 "H" or "L" Hyper Page Mode (EDO) Read Cycle (OE Control) Semiconductor Group 19 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS UCAS LCAS VIL tCSH tASR tRAH tASC AAA AAA AAA tRAL tCAH tASC tCAH tASC tCAH AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA Address V AAAAA IH AAAAA AAAAA VIL AAAAA AAAAA AAAAA AAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tRAD tAA tAA tRCH tRRH tRCH tRCS AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS WE VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tRCH tRCS tWPZ tOES V tCAC tCPA tWPZ tCAC tCPA tOFF AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA OE AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA tRAC tAA tCAC I/O IH (Output) V IL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA tOEZ tWEZ AAA AAA AAA AAA AAA AAA AAA tWEZ AAAA AAAA AAAA AAAA AAAA AAAA AAAA V tCLZ AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Data Out 1 Data Out 2 Data Out N WL7 "H" or "L" Hyper Page Mode (EDO) Read Cycle (WE Control) Semiconductor Group 20 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS UCAS LCAS VIL tCSH tASR tRAH tASC AAA AAA AAA AAA AAA AAA tRAL tCAH tASC tCAH AAAAAAAAA tASC tCAH AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA Address V AAAAA IHAAAAA Row AAAAA AAAAA VIL AAAAA Addr AAAAA AAAAAAAAAA AAAAAAAAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAA Column N AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA tRAD tCWL tWCS VIH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA tCWL tWCH tWP tWCS tRWL tCWL tWCH tWP tWCH tWCS tWP AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA WE AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA V OE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS V IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA tDH AAAAAAAAAA tDS tDH AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA tDS tDH AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA I/O (Input) V IL AAAAAAAAAA AAAAAAAAAA Data In 1 AAAAAAAAAA Data In 2 AAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA Data In N AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL8 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group 21 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRAS V IH tRP tRCD tRSH tCP tCAS tCP tCAS tCRP RAS VIL tHPC tCRP V IH tCAS UCAS LCAS VIL tCSH tASR tRAH tASC AAA AAA tRAL tCAH tASC tCAH tASC tCAH AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAA V Address IH AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA VIL AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Row AAA Column 1 AAAAAAAAAA Column 2 AAAAAAAAAA Column N AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA tRAD tCWL tRCS tCWL tRCS tCWL tRWL tRCS WE VIH AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tWP tOEH OE V OH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA OL AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tWP tOEH AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tWP tOEH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA tODD tDS AAAA AAAA AAAA AAAA AAAA AAAA AAAA tODD tDS AAAA AAAA AAAA AAAA AAAA AAAA AAAA tDS tODD I/O (Input) V IH VIL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tDH tDH tDH Data In 1 Data In 2 Data In N WL16 "H" or "L" Hyper Page Mode (EDO) Late Write Cycle Semiconductor Group 22 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tCPWD tCWD tAWD tOEA tOEA tCAH tRWD tCWD tAWD tOEA tCSH AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tWP Data In tOEZ tDH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column tCPA tCLZ AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tWP Data In tDH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Column AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tASC tCWL tOEH tDZC tCAC tAA tCAH tCPA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tWP tRSH Data In tDH tDS AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tRP tCRP tASR Row tRAL tRWL tCWL tODD tCAS tCLZ tRASP tPRWC tCAS tODD tCPWD tCWD tOEZ tAWD tASC tDZC AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tCWL tCP tOEH tAA AAAAAA AAAAAA AAAAAA AAAAAA tODD tCAS tRAD tRAH AAAAA AAAAA AAAAA AAAAA AAAAA I/O (Inputs) V IL OH I/O (Outputs) V IH IH IH IH IH IH V IL V IL V IL V IL V V IL V V V Address UCAS LCAS RAS V WE OE V V OL WL17 AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tCAH tDZC tCLZ tDZO Column tASC tAA tCAC AAAAAA AAAAAA AAAAAA AAAAAA tRCS AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA tRCD Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group tASR Row 23 tRAC Data Out AAAAA AAAAA AAAAA tDS Data Out AAAAA AAAAA AAAAA tDS Data Out AAAAA AAAAA AAAAA tOEH HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS V tRP RAS IH VIL tCRP tRPC UCAS LCAS V IH AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA VIL tRAH tASR tASR Row V Address IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA VIL AAAAAAAAAAAA AAAAAAAAAAAA Row AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH I/O (Outputs) V OL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA V HI-Z "H" or "L" WL9 RAS Only Refresh Cycle Semiconductor Group 24 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRP V tRAS tRP RAS IH VIL tRPC tCP tCSR tCHR tRPC tCRP AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA V UCAS LCAS IH VIL tWRP tWRH V AAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE VIL tOEZ V OE IH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD IH I/O (Inputs) V IL V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD OH I/O (Outputs)VOL V HI-Z tOFF AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL10 CAS-before-RAS Refresh Cycle Semiconductor Group 25 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC V tRC tRP tRAS tRP tRAS IH RAS VIL tRCD V tRSH tCHR tCRP UCAS LCAS IH VIL tRAD tASC tASR tRAH AAAAA AAAAA AAAAA AAAAA tWRP tCAH tWRH tASR Row AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAA IHAAAAAAA AAAAAAA AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRCS WE V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA tRRH AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tDZO V tODD tCAC tCLZ AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA I/O (Inputs) IH VIL AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA tOFF tOEZ Valid Data Out tRAC OH I/O (Outputs) V OL AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA V AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA HI-Z "H" or "L" WL11 Hidden Refresh Read Cycle Semiconductor Group 26 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRP V IH tRC tRAS tRP tRAS RAS VIL tRCD V IH tRSH tCHR tCRP UCAS LCAS VIL tRAD tRAH tASR tASC tCAH tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Address V AAAAAAA IHAAAAAAA AAAAAAA AAAAA AAAAA AAAAAAA Row AAAAA AAAAA AAAAAAA AAAAA VIL AAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row tWCS tWCH tWP tWRP AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA tWRH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V WE AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA tDS I/O (Input) V AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA IL AAAAAAAAAAAAAAA tDH Valid Data AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH I/O (Output) V OL V HI-Z AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL12 Hidden Refresh Early Write Cycle Semiconductor Group 27 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP V tRASS tRPS RAS IH VIL tRPC tCSR V tCHS tCRP AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA tCP IH UCAS LCAS VIL tWRP tWRH V WE IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OE IH VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD IH I/O (Inputs) V IL V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD tOEZ OH I/O (Outputs) VOL V HI-Z tOFF AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA "H" or "L" WL13 Self Refresh (Sleep Mode) Semiconductor Group 28 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Package Outlines Plastic Package P-TSOPII-50 (400 mil) (Thin Small Outline, SMD) Semiconductor Group 29 |
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